RTL Design Engineer, Machine Learning
Company: Google
Location: Sunnyvale
Posted on: April 4, 2026
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Job Description:
Minimum qualifications: Bachelor's degree in Electrical
Engineering, Computer Engineering, Computer Science, or a related
field, or equivalent practical experience. 8 years of experience
with custom silicon design (SoCs, ASICs, etc.). Experience with RTL
(Register Transfer Level) design using Verilog or SystemVerilog.
Preferred qualifications: Master's degree or PhD in Electrical
Engineering, Computer Engineering or Computer Science, with an
emphasis on computer architecture. Experience interacting with
software, architecture, and other cross-functional teams.
Experience with a scripting language (e.g., Python or Perl).
Experience applying engineering best practices (e.g., code review,
testing, refactoring). Knowledge of processor design, accelerators,
or memory hierarchies and machine learning algorithms. Knowledge of
high performance and low power design techniques. About the job In
this role, you’ll work to shape the future of AI/ML hardware
acceleration. You will have an opportunity to drive cutting-edge
TPU (Tensor Processing Unit) technology that powers Google's most
demanding AI/ML applications. You’ll be part of a team that pushes
boundaries, developing custom silicon solutions that power the
future of Google's TPU. You'll contribute to the innovation behind
products loved by millions worldwide, and leverage your design and
verification expertise to verify complex digital designs, with a
specific focus on TPU architecture and its integration within
AI/ML-driven systems. The AI and Infrastructure team is redefining
what’s possible. We empower Google customers with breakthrough
capabilities and insights by delivering AI and Infrastructure at
unparalleled scale, efficiency, reliability and velocity. Our
customers include Googlers, Google Cloud customers, and billions of
Google users worldwide. We're the driving team behind Google's
groundbreaking innovations, empowering the development of our AI
models, delivering unparalleled computing power to global services,
and providing the essential platforms that enable developers to
build the future. From software to hardware our teams are shaping
the future of world-leading hyperscale computing, with key teams
working on the development of our TPUs, Vertex AI for Google Cloud,
Google Global Networking, Data Center operations, systems research,
and much more. The US base salary range for this full-time position
is $163,000-$237,000 bonus equity benefits. Our salary ranges are
determined by role, level, and location. Within the range,
individual pay is determined by work location and additional
factors, including job-related skills, experience, and relevant
education or training. Your recruiter can share more about the
specific salary range for your preferred location during the hiring
process. Please note that the compensation details listed in US
role postings reflect the base salary only, and do not include
bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities Understand the overall application of the chip,
proposing and developing improvements in overall design. Design and
document one or more blocks of an ASIC, including functionality and
timing. Work closely with Software teams on functionality,
interfaces, and documentation.
Keywords: Google, Elk Grove , RTL Design Engineer, Machine Learning, Engineering , Sunnyvale, California
